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Integrated Circuit Systems, Inc.
ICS9179-16
Preliminary Product Preview
Zero Delay Buffers
General Description
The ICS9179-16 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a zero delay buffer device, using an internal PLL. This buffer can be used for phase synchronization to a master clock. With the wide PLL loop BW, this buffer is compatible to Spread Spectrum input clocks. The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed. The device defaults to zero-delay mode, but can be programmed with I2C for selectable delays -2.7, +2.0, -0.7 ns (nominal target values).
Features
* * * * * * * * * * * *
Zero delay buffer, 16 outputs Supports up to four SDRAM DIMMS Wide PLL loop bandwidth makes this part ideal in Spread Spectrum applications. Skew Input to FB_IN 250ps default, with selectable skew -2.7, +2.0, -0.7ns nominal. Synchronous clocks skew matched to 250 ps window on output. 33 to 133MHz input or output frequency. I2C Serial Configuration interface to allow individual clocks to be stopped, or selectable delays. Multiple VDD, VSS pins for noise reduction Slew rate 1.5V/ns into 30pF. VDD = 3.3 5%, 0 to 70C All outputs (0:15) tristate with OE low (FB_OUT stays running). 48-Pin SSOP package
Block Diagram
Pin Configuration
Functionality
OE# 0 1
0557A--03/15/02
OUTPUT (0:15) Hi-Z 1 X INPUT
FB_OUT 1 X INPUT 1 X INPUT
48-Pin SSOP
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PentiumPro is a trademark of Intel Corporation. I 2C is a trademark of Philips Corporation.
ICS9179-16
ICS9179-16
Preliminary Product Preview
Pin Descriptions
PIN NUMBER 2 5, 6, 9, 10 15, 16, 19, 20 29, 30, 33, 34 40, 41, 44, 45 12 13 24 25 37 3, 7, 11, 17, 21, 31, 35, 38, 42, 46 4, 8, 14, 18, 28, 32, 36, 39, 43, 47 22 23 26 27 1, 48 P I N NA M E OE OUTPUT (0:3) OUTPUT (4:7) OUTPUT (8:11) OUTPUT (12:15) INPUT FB_IN SDATA SCLK FB_OUT VDD GND VDDA VDDS GNDS GNDA N/C TYPE IN OUT OUT OUT OUT IN IN I/O I/O OUT PWR PWR PWR PWR PWR PWR DESCRIPTION Tri-states all outputs except FB_OUT when held LOW. Has internal pull-up.2 SDRAM Byte 0 clock outputs1 SDRAM Byte 1 clock outputs1 SDRAM Byte 2 clock outputs1 SDRAM Byte 3 clock outputs1 Input for reference clock. Feedback input. D a t a p i n f o r I 2C c i r c u i t r y 3 C l o c k p i n f o r I 2C c i r c u i t r y 3 Feedback output to input FB_IN. 3.3V Power supply for output buffers Ground for output buffers 3.3V Power supply for Analog PLL stages 3.3V Power supply for I2C circuitry G r o u n d f o r I 2C c i r c u i t r y Ground for Analog PLL stages Pins are not internally connected
Notes: 1. At power up all sixteen outputs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility. 4. I2C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0 5. Subject to design engineering verification of target value.
Delay Selection Table4 Power Groups
VDD = Power supply for OUTPUT buffers VDDS = Power supply for I2C circuitry VDDA = Power supply for Analog PLL circuitry
INPUT Control Byte0 bit1 0* 0 1 1
FB_IN Control Byte0 bit0 0* 1 0 1
Nominal Target5 Delay, INPUT to FB_IN pins. 0ns -2.7ns +2.0ns -0.7ns
Ground Groups
GND = Ground supply for OUTPUT buffer GNDS = Ground supply for I2C circuitry GNDA = Ground supply for Analog PLL circuitry
2
ICS9179-16
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controler (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 3
6.
ICS9179-16
Preliminary Product Preview
ICS9179-16 Power Management
The values below are estimates of target specifications.
Condition No Clock Mode (BUF_IN - VDD1 or GND) I2C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 100MHz (BUF_IN = 100.00MHz)
Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND 30mA 150mA 180mA
Byte 2: OUTPUT Clock Register (Default = 1)
BIT PIN# PWD Bit 7 45 1 Bit 6 44 1 Bit 5 41 1 Bit 4 40 1 Bit 3 34 1 Bit 2 33 1 Bit 1 30 1 Bit 0 29 1 DESCRIPTION OUTPUT 15 (Act/Inact) OUTPUT 14 (Act/Inact) OUTPUT 13 (Act/Inact) OUTPUT 12 (Act/Inact) OUTPUT 11 (Act/Inact) OUTPUT 10 (Act/Inact) OUTPUT 9 (Active/Inactive) OUTPUT 8 (Active/Inactive)
Byte 3: OUTPUT Clock Register
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (default = 0)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 12 Bit 02 PIN# 12 13 PWD 0 0 0 0 0 0 0 0 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d Clock INPUT Skew Control FBIN Skew Control
Byte 1: OUTPUT Clock Register
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 20 1 19 1 16 1 15 1 10 1 9 1 6 1 5 1
DESCRIPTION OUTPUT 7 (Act/Inact) OUTPUT 6 (Act/Inact) OUTPUT 5 (Act/Inact) OUTPUT 4 (Act/Inact) OUTPUT 3 (Act/Inact) OUTPUT 2 (Act/Inact) OUTPUT 1 (Act/Inact) OUTPUT 0 (Act/Inact)
Notes: 2 = Default = 0; 1 = Delay element enabled, 0 = No delay path.
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
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ICS9179-16
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Output Disabled Supply Current Input frequency Input Capacitance
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD IDD Fi CIN
CONDITIONS
MIN 2 VSS-0.3 -5 -60
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M VDD = 3.3 V; All Outputs Loaded Logic Inputs
-33 115 170
33
MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 150 mA 180 mA 30 mA 30 mA 105 MHz 5 pF
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Supply Current Input frequency Input Capacitance
1
SYMBOL VIH VIL IIH IIL IIL IDD1 IDD2 Fi 1 CIN1
CONDITIONS
MIN 2 VSS-0.3 -5 -60
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with 100K pull-up resistors CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M VDD = 3.3 V; All Outputs Loaded Logic Inputs
-33 115 170
MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 150 mA 180 mA 150 5 MHz pF
10
Guarenteed by design, not 100% tested in production.
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ICS9179-16
Preliminary Product Preview
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO3 VO = VDD*(0.5) Output Impedance RDSP3 Output Impedance RDSN3 VO = VDD*(0.5) Output High Voltage VOH3 IOH = -30 mA IOL = 23 mA Output Low Voltage VOL3 Output High Current IOH3 VOH = 2.0 V VOL = 0.8 V Output Low Current IOL3 Rise Time Tr3 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Fall Time Tf3 Duty Cycle Dt3 VT = 1.5 V Output to Output Tsk3 VT = 1.5 V Skew Window VT = 1.5 V default Zero delay I2 C Tskd1 B0 bits 0, 1 = 00 1, 2 Tskd2 VT = 1.5 V bits 0, 1 = 10 IN to FB_IN Skew Tskd3 VT = 1.5 V bits 0, 1 = 01 VT = 1.5 V bits 0, 1 = 11 Tskd4 MIN 33 10 10 2.6 TYP MAX UNITS 133 MHz 24 Ohm 24 Ohm V 0.4 V -54 mA mA 1.33 nS 1.33 nS 55 % 250 -250 -2.2 +1.5 -0.2 0 -2.7 +2.0 -0.7 250 -3.2 +2.5 -1.2 pS pS nS nS nS
40
45
Notes: 1. Guarenteed by design, not 100% tested in production 2. Delay elements FBIN and clock INPUT path are selected by I2C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT Control. (Default is 0). A 0 = No delay in path, 1 = Delay element selected. Note: PWD = Power-Up Default
Input Pulse
MIN Input Pulse Low Time Input Pulse High Time Tim-Low Tim-High Vpulse_Low 0.8V Vpulse_High 2.0V 1.0 1.5 TYP MAX UNITS ns ns
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ICS9179-16
Preliminary Product Preview
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs.
Capacitor Values: All unmarked capacitors are 0.01F ceramic
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ICS9179-16
Preliminary Product Preview
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC MIN. .620 D NOM. .625 N MAX. .630 48
Ordering Information
ICS9179F-16
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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